Jaspreet Singh (Entry No: 2013EEZ2812)
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Design and Analysis of 4H-SiC based planar Junctionless FETs for sub-10nm regime.
Electrical Engineering
July 12, 2023
9:30 am
Control Lab (II / 214), IIT Delhi
Internal Supervisors: M Jagadesh Kumar
Internal Supervisor 2:
External Supervisor:
Internal Supervisor 2:
External Supervisor: