Navneet Kaur (Entry No: 2017EEZ8569)
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Design and Optimization of Emerging Nanotube Tunnel FETs for the Implementation of Low-Power Ternary Logic
Department of Electrical Engineering
June 19, 2026
1:00 pm
Online
Internal Supervisors: Anuj Dhawan
Internal Supervisor 2: M Jagadesh Kumar
External Supervisor: Dr. Raghvendra Saxena
Internal Supervisor 2: M Jagadesh Kumar
External Supervisor: Dr. Raghvendra Saxena